library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity logics is
generic (N : integer := 4);
port(	data_reg  : in  std_logic_vector (N-1 downto 0);
		immediate : in  std_logic_vector (N-1 downto 0);
		op_type   : in  std_logic_vector (1 downto 0);
		data_out  : out std_logic_vector (N-1 downto 0)
);
end logics;

architecture Behavioral of logics is
begin

process(data_reg,immediate,op_type)
variable number : std_logic_vector (N-1 downto 0);
begin
	case op_type is
		when "00" => -- AND
			for i in 0 to N-1 loop
				number(i) := (data_reg(i) and immediate(i));
			end loop;
		when "01" => -- OR
			for i in 0 to N-1 loop
				number(i) := (data_reg(i) or immediate(i));
			end loop;
		when "10" => -- XOR
			for i in 0 to N-1 loop
				number(i) := (data_reg(i) xor immediate(i));
			end loop;
		when others =>
			number := (others => '0');
	end case;

	data_out <= number;

end process;

end Behavioral;

